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| Company | Category | HQ | Latest Node | 2026 Cap-Ex | Latest Move | Updated |
|---|---|---|---|---|---|---|
| NVIDIA | Fabless | Santa Clara, US | TSMC N3B | $20B+ | GB300 Blackwell Ultra volume ramp — CoWoS-L allocation sold out through Q3 | 1h ago |
| Intel | IDM | Santa Clara, US | Intel 18A | $25B | Panther Lake 18A tape-in complete; Clearwater Forest EUV milestone hit | 3h ago |
| TSMC | Foundry | Hsinchu, TW | N2 / N1.6 | $38B | Arizona Fab 22 Phase 2 N2 groundbreaking; CoWoS capacity expanding +40% | 2h ago |
| AMD | Fabless | Santa Clara, US | TSMC N3E | $12B | MI400 architecture confirmed for 2H 2026; CDNA 4 ramp on schedule | 4h ago |
| Samsung Semiconductor | IDM | Suwon, KR | SF2 / SF1.4 | $22B | Taylor TX SF2 yield issues delay major customer tape-out by 2 quarters | 6h ago |
| SK Hynix | Memory | Icheon, KR | HBM4 16-stack | $18B | HBM4 16-stack passed NVIDIA qualification; sole supplier through Q2 2027 | 2h ago |
| ASML | Equipment | Veldhoven, NL | High-NA EUV | $10B | NXE:3600D High-NA backlog 14 units; TSMC delivery confirmed Q4 2026 | 5h ago |
| Micron Technology | Memory | Boise, US | 1-gamma DRAM | $14B | Idaho greenfield fab Phase 1 breaks ground; HBM4 sampling begins Q4 2026 | 8h ago |
| Qualcomm | Fabless | San Diego, US | TSMC N3E | $6B | Snapdragon 8 Elite Gen 2 tape-out confirmed; 3 PC OEM wins announced | 9h ago |
| Apple | Fabless | Cupertino, US | TSMC N2P | $20B | A20 on N2P confirmed for iPhone 18; locked 60% of TSMC N2 capacity 2026 | 7h ago |
| Arm Holdings | IP | Cambridge, UK | N/A | $3B | Cortex-X9 licensee count hits 11; CSS-2026 platform — 8 chip companies signed | 11h ago |
| Broadcom | Fabless | Palo Alto, US | TSMC N2 | $15B | XPU revenue run-rate crosses $4B/yr; Google TPU v6 in volume production | 12h ago |
| SMIC | Foundry | Shanghai, CN | N+2 (7nm equiv) | $7.5B | ████████████████████████████ | locked |
| Applied Materials | Equipment | Santa Clara, US | N/A | $6B | ████████████████████████████ | locked |
| Synopsys | EDA | Sunnyvale, US | N/A | $2.8B | ████████████████████████████ | locked |
| TSMC Packaging | Packaging | Hsinchu, TW | SoIC / CoWoS-L | $8B | ████████████████████████████ | locked |
Original analysis sourced from SEC filings, fab disclosures, patent databases, and earnings calls. Updated daily.
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16-stack HBM4 yields at three vendors — and why the gap between first and third is wider than any previous HBM generation transition. Supply implications for MI400.
Reading between the lines of Intel's process milestone. Three external analysts weigh in on what "tape-in complete" means for the 2H 2026 volume ramp timeline.
The NXE:3600D delivery schedule, tool productivity at TSMC's Fab 18, and the exposure-dose challenge that keeps process engineers up at night.
Broadcom's $4B XPU run-rate is just the visible tip. We map six undisclosed hyperscaler ASIC programs currently in tape-out at TSMC and Samsung.
N2, N3, HBM4, and Intel 18A are absorbing the majority of global cap-ex. The full breakdown by company, geography, and application target.
Forecasts grounded in fab data, patent filings, and observable deal flow. Explicit confidence intervals. Conservative/likely/aggressive scenarios.
Samsung SF2 yield struggles and Intel 18A's slow external customer ramp leave TSMC with structural share dominance through N1.6. Only a credible 2nm-class equivalent from either challenger by late 2028 changes this.
GB300 and MI400 both require 16-stack HBM4. Combined NVIDIA + AMD demand exceeds total qualified supply through Q2 2027. SK Hynix gets first allocation; Micron online by Q3 2027.
CoWoS-L, SoIC, Foveros Direct, and EMIB are where performance is won. Every leading-edge chip in 2028 is a packaging story as much as a process node story. Substrate capacity will constrain 5+ major product launches.
Hyperscaler XPU spend, sovereign AI chip programs (EU, India, UAE, Saudi), and edge inference ASICs drive acceleration. Broadcom, Marvell, and 3 undisclosed startups are the primary beneficiaries in this window.
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